Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various middle of line (MOL) flow for fabricating high density finFET devices having cross couple.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be positioned to a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. FinFETs generally have the increased channel widths, which includes channel portions formed on the sidewalls and top portions of the fins. Since drive currents of the finFETs are proportional to the channel widths, finFETs generally display increased drive current capabilities.
Designers are constantly attempting to increase the density of integrated circuits by decreasing the size of features on semiconductor devices. As a result, there is challenge to create standard functional cell library logic devices, such as scan-D flip-flops and multiplexers to accommodate the smaller devices. This is particularly the case at the 10 nm node, where lithographic limitations can result in a lack of scaling of standard cell library devices. One solution attempted by designers is to perform cross coupling of transistors for providing standard cell library devices. Cross coupling and logic scaling provides for utilizing lower amount of area of the semiconductor device, in an attempt to overcome undesirable properties, such as larger semiconductor device or less functionality in the semiconductor device.
As finFET devices become more dense (e.g., 10 nm technology), the tracks (i.e., metal pitch) become smaller. This raises many issues, such as processing accurately at 7.5 nm track spaces. In a 7.5T design, in a standard cell, at 42 nm spacing per track, only 315 nm are generally available. Generally 42 nm is typically selected as a limit to allow for printing using Self-Aligned Double Patterning (SADP) at various sizes, as would be required for Static Random Access Memory (SRAM) Metal 2 Word Lines (M2 WL) and potential sizing usage in logic routing levels.
Accordingly, roughly 90-95 nm Power Rail (PR) width and 215 nm space would be available for the designers to perform placing and routing. One of the more critical parts of the design may be processing the M0 metal Tip to Tip (T2T)—as in controlling precisely during manufacturing the end-to-end spacing between two Metal 0 line segments—and the CB enclosure by M0 with CB the metal via electrically connecting M0 to the top of the gate. The industry lacks an effective method of providing a design that comprises cross coupling and a first level metal needed to finish a standard cell, wherein the first level metal can be used as the routing level.
The present disclosure may address and/or at least reduce one or more of the problems identified above.